Average Senior ASIC Design Engineer with Verilog VHDL Skills Salary in San Jose, California

$129,587
Avg. Base Salary (USD)
25%
$110k
MEDIAN
$130k
75%
$150k

The average salary for a Senior ASIC Design Engineer is $129,587 in 2025

Base Salary
$110k - $150k
Bonus
$11k - $25k
Profit Sharing
$0 - $8k
Total Pay
$115k - $177k
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FAQs About Senior ASIC Design Engineers

What is the highest pay for Senior ASIC Design Engineers in San Jose?

Our data indicates that the highest pay for a Senior ASIC Design Engineer in San Jose is $NaN / year

What is the lowest pay for Senior ASIC Design Engineers in San Jose?

Our data indicates that the lowest pay for a Senior ASIC Design Engineer in San Jose is $NaN / year

How can Senior ASIC Design Engineers increase their salary?

Increasing your pay as a Senior ASIC Design Engineer is possible in different ways. Change of employer: Consider a career move to a new employer that is willing to pay higher for your skills. Level of Education: Gaining advanced degrees may allow this role to increase their income potential and qualify for promotions. Managing Experience: If you are a Senior ASIC Design Engineer that oversees more junior Senior ASIC Design Engineers, this experience can increase the likelihood to earn more.